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EECS 388 - Computer Systems & Assembly Language

The Xilinx/Digilent XUP-V2P Development Board (Courtesy of Xilinx/Digilent)

Course Description

"Internal organization of microprocessor and microcontroller systems; programming in assembly language; input and output system; controlling external devices. The course will focus on one or two specific microprocessors and computer systems."

This class will make use of the Xilinx/Digilent XUP-V2P (XUP-V2Pro) Development Board. This development board contains a modern Virtex-II Pro Platform FPGA along with various peripherals such as Ethernet, USB, Audio In/Out, LEDs, buttons, switches, VGA, etc. Various System-On-Chip (SoC) architectures will be developed during this class, all of which will be implemented within the fabric of the FPGA. Most, if not all, of the SoCs developed during this class will use the MicroBlaze processor; a soft 32-bit processor core developed by Xilinx. The instruction set architecture, or ISA, of the MicroBlaze will be studied and used throughout this class, in order to teach students the relationships between high-level languages, assembly language, and the actual hardware implementation of computer systems.

Resources

This class will focus on using Xilinx Platform FPGAs along with the associated Xilinx EDK toolset (XPS + ISE). Much of the class materials can be found online on either this website and/or the Xilinx homepage. All of the class projects will make use of the XUP-V2P (XUP-V2Pro) development board which contains a Xilinx Virtex-II Pro 30 FPGA.

Documentation Repository

Lab Instructions

• Image:ReportFormat.pdf - EECS 388 Lab Report Format & Instructions

Basic Information

• Xilinx XUP-V2P Home Page (Good starting point for XUP documentation)
• XUP-V2P User Constraints Files (UCFs)
• MicroBlaze Processor Reference Guide (ISA Documentation, etc.)
• MicroBlaze Software Reference Guide (How to build SW for MB, etc.)
• Xilinx XST 9.x User's Guide (Good HDL coding templates and tips)

EDK 9.1 Information

• Description of EDK/XPS Project Files
• EDK 9.1 Reference Manual
• EDK 9.1 MicroBlaze Tutorial (NOTE - for a Spartan FPGA)
• EDK 9.1 PowerPC Tutorial (NOTE - for a Virtex-4 FPGA)

Examples (XAPPs)

• xapp967 - Creating an OPB IPIF-based IP and Using it in EDK
• xapp778 - Using and Creating Interrupt-Based Systems
• xapp529 - Connecting Customized IP to the MicroBlaze Processor Using Fast Simplex Link (FSL) Channels
• xapp730 - Getting Started with uClinux on the MicroBlaze Processor

ChipScope Pro Information

• HOWTO - Instantiating ChipScope Pro Cores within EDK
• HOWTO - Debugging HW with ChipScope Pro
• HOWTO - Monitoring HW Signals with ChipScope Pro

Lecture Schedule

All lectures can be found through the following link: EECS 388 Lecture Page.

Lab Repository

All lab projects can be found through the following link: EECS 388 Lab Page.

Homework

Assignments

• Image:Homework1.pdf - HW #1, due September 19, 2007
• Image:Homework2.pdf - HW #2, due September 26, 2007
• Image:Homework3.pdf - HW #3, due October 17, 2007
• Image:Homework4.pdf - HW #4 due October 31, 2007
• Image:Homework5.pdf - Updated: HW #5 due December 5, 2007

Solutions

These will be posted as the semester goes on.

Copyright

All lab materials created by Jason Agron (Summer, 2007). Feel free to use the labs for educational purposes, but please give credit to Jason and the CSDL lab at the University of Kansas.