Publications

From Hybridthreads Wiki

Contents 1 2009 2 2008 3 2007 4 2006 5 2005 6 2004 7 2003

2009

• Jason Agron and David Andrews, Building Heterogeneous Reconfigurable Systems With a Hardware Microkernel. Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS, Grenoble, France, October 2009. Presentation (PDF)

• Jason Agron and David Andrews, Hardware Microkernels for Heterogeneous Manycore Systems. Proceedings of the First International Workshop on Real-time Systems on Multicore Platforms: Theory and Practice (XRTS) held in conjunction with the 38th International Conference on Parallel Processing (ICPP), Vienna, Austria, September 2009.

• Jason Agron and David Andrews, Building Heterogeneous Reconfigurable Systems Using Threads. Proceedings of the 19th International Conference on Field Programmable Logic and Applications (FPL), Prague, Czech Republic, September 2009.

• Jason Agron, Domain-Specific Language for HW/SW Co-Design for FPGAs (PRE-PRINT). Proceedings of the IFIP Working Conference on Domain Specific Languages (DSL WC), Volume 5658 of Lecture Notes in Computer Science, pages 262-284. Springer-Verlag, July, 2009.

• William Harrison, Adam Procter, Jason Agron, Garrin Kimmell, and Gerard Allwein, Model-driven Engineering from Modular Monadic Semantics: Implementation Techniques Targeting Hardware and Software (PRE-PRINT). Proceedings of the IFIP Working Conference on Domain Specific Languages (DSL WC), Volume 5658 of Lecture Notes in Computer Science, pages 20-44. Springer-Verlag, July, 2009.

• Jason Agron and David Andrews, Hardware Microkernels for Heterogeneous Manycore Systems. Proceedings of the Fifth International Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT), Dublin, Ireland, June, 2009.

2008

• D. Andrews, Increasing Design Productivity for Next Generation Platform FPGA's , Presentation at the ICFPT08 Pre-Workshop on FPGA Design Productivity, December 2008

• D. Andrews, J. Agron, Modeling Abstractions for Next-Generation Reconfigurable Computing, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) July 2008

• Santner, S., Peck, W., Agron, J., and Andrews, D., Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs, Proceedings of the 4th International Workshop on Applied Reconfigurable Computing (ARC 2008) in Lecture Notes in Computer Science, Springer-Verlag, Number 4943, pp. 99 - 110, 2008

• Elias Teodoro Silva Jr., David Andrews, Carlos Eduardo Pereira, and Flavio Rech Wagner An Infrastructure for Hardwdare-Software Co-Design of Embedded Real-Time Java Applications, Proceedings of the 11th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2008) pp. 273-280, May 2008.

• D. Andrews, R. Sass, E. Anderson, J. Agron, W. Peck, J. Stevens, F. Baijot, and E. Komp, Achieving Programming Model Abstractions For Reconfigurable Computing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 1, pp. 34–44, January 2008.

2007

• Thamer Abuyasin, Enabling Task Level Parallelism In Handel-C, Master's Thesis at the University of Kansas (December, 2007). Thesis and presentation slides.

• Erik Anderson, Wesley Peck, Jim Stevens, Jason Agron, Fabrice Baijot, Seth Warn, and David Andrews, Supporting High-Level Language Semantics Within Hardware Resident Threads, 17th International Conference on Field Programmable Logic and Applications, August 2007. pp. 98-103.

• Jim Stevens, Hybridthreads Compiler: Generation of Application Specific Hardware Thread Cores from C, Ph.D. Forum at the 17th International Conference on Field Programmable Logic and Applications, August 2007.

• Erik Anderson, Abstracting the Hardware/Software Boundary through a Standard System Support Layer and Architecture, Ph.D. Dissertation at the University of Kansas (May, 2007). Thesis and presentation slides.

• Erik Anderson, Wesley Peck, Jim Stevens, Jason Agron, Fabrice Baijot, Seth Warn, and David Andrews, Memory Hierarchy for MCSoPC Multithreaded Systems, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) June 2007.

• Ron Sass, William V. Kritikos, Andrew G. Schmidt, Srinivas Beeravolu, Parag Beeraka, Kushal Datta, David Andrews, Richard S. Miller, and Daniel Stanzione, Jr. Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale Computing, Proceedings of the Fifteenth Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA. April 2007.

2006

• Jason Agron, Wesley Peck, Erik Anderson, David Andrews, Ed Komp, Ron Sass, Fabrice Baijot, and Jim Stevens, Run-Time Services for Hybrid CPU/FPGA Systems on Chip, Proceedings of the 27th IEEE International Real-Time Systems Symposium, Rio De Janeiro, Brazil, December 2006 pp. 3 - 12. Image:Rtss06.pdf

• Wesley Peck, Erik Anderson, Jason Agron, Jim Stevens, Fabrice Baijot, and David Andrews, Hthreads: A Computational Model for Reconfigurable Devices, Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL) August 2006. pp. 885-888 Image:Fpl06.pdf

• David Andrews, Ron Sass, Erik Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot and Ed Komp,, The Case for High level Programming Models for Reconfigurable Computers, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) June 2006. Image:Ersa06.pdf

• Jason Agron, Run-Time Scheduling Support for Hybrid CPU/FPGA SoCs, Master's Thesis at the University of Kansas (April, 2006). Thesis and presentation Slides

• Erik Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp, Ron Sass, David Andrews, Enabling a Uniform Programming Model Across the Software/Hardware Boundary, Proceedings of the The Fourteenth Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, CA, 24-26 April 2006. Image:Fccm06.pdf

2005

• Razali Jidin, Extending the Thread Programming Model Across Hybrid FPGA/CPU Architectures, Ph.D. Dissertation at the University of Kansas (April, 2005). Thesis and presentations slides

• David Andrews, Wesley Peck, Jason Agron, Keith Preston, Ed Komp, Mike Finley, Ron Sass, hthreads: A Hardware/Software Co-Designed Multithreaded RTOS Kernel, Proceedings of the 10th IEEE International Conference on Emerging Technologies and Factory Automation Facolta' di Ingegneria, Catania, Italy, 19-22 September 2005. Image:Etfa05.pdf

• David Andrews, Iain Bate, Thomas Nolte, Clara M. Otero Perez, Stefan M. Petters, Impact of Embedded Systems Evolution on RTOS Use and Design, Proceedings of the 1st International Workshop Operating System Platforms for Embedded Real-Time Applications (OSPERT'05) in conjunction with the 17th Euromicro International Conference on Real-Time Systems (ECRTS'05), p 13-19, Palma de Mallorca, Balearic Islands, Spain. Image:Ospert.pdf

• R. Jidin, D. Andrews, W. Peck, D. Chirpich, K. Stout, J. Gauch, Evaluation of the Hybrid Multithreading Programming Model using Image Processing Transform, Proceedings of the 12th Reconfigurable Architectures Workshop (RAW 2005), April 4-5, 2005, Denver, Colorado, USA. Image:Hwimage.pdf

2004

• W. Peck, J. Agron, D. Andrews, M. Finley, E. Komp, Hardware/Software Co-Design of Operating System Services for Thread Management and Scheduling, In Proceedings of the 25th IEEE International Real-Time Systems Symposium, Works In Progress Session (RTSS, WIP 2004). Lisbon, Portugal, December 5-8, 2004. Image:RTSS wesley.pdf

• J. Agron, D. Andrews, M. Finley, E. Komp, W. Peck, FPGA Implementation of a Priority Scheduler Module, In Proceedings of the 25th IEEE International Real-Time Systems Symposium, Works In Progress Session (RTSS, WIP 2004). Lisbon, Portugal, December 5-8, 2004. Image:RTSS FPGA Scheduler.pdf

• R. Jidin, D. Andrews, D. Niehaus, W. Peck, Fast Synchronization Primitives for Hybrid CPU/FPGA Multithreading, In Proceedings of the 25th IEEE International Real-Time Systems Symposium, Works In Progress Session (RTSS, WIP 2004). Lisbon, Portugal, December 5-8, 2004. Online Proceedings (Pages 27-31)

• Andrews, D., Niehaus, D., Jidin, R., Finley, M., Peck, W., Frisbee, M., Ortiz, J. Komp, E., Ashenden, P., Programming Models for Hybrid FPGA/CPU Computational Components: A Missing Link, IEEE Micro, July/August 2004. Image:Micro.pdf

• Jidin, R., Andrews, D., Niehaus, D., Implementing Multi Threaded System Support for Hybrid Computational Components, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), June 2004, Las Vegas, Nevada. Image:ERSA2004.pdf

• Andrews, D., Niehaus, D., Jidin, R., Implementing the Thread Programming Model on Hybrid FPGA/CPU Computational Components, Proceedings of the 1st Workshop on Embedded Processor Architectures (WEPA) held in conjunction with the International Symposium on Computer Architecture, February, 2004, Madrid, Spain. Image:Wepa.pdf

• Andrews, D., Niehaus, D., and Ashenden, P., Programming Models for Hybrid FPGA/CPU Computational Components, IEEE Computer, January 2004. Image:Computer.pdf

• Michael Finley, Hardware/Software Codesign: Thread Manager, Master's Thesis at the University of Kansas (December, 2004). Thesis and presentation slides

2003

• Niehaus, D. , Andrews, D., Using the Multi-Threaded Computation Model as a Unifying Framework for Hardware-Software Co-Design and Implementation, Proceedings of the 9th International Workshop on Object-oriented Real-time Dependable Systems (WORDS 2003). Image:Ku-words.pdf

• David Andrews and Douglas Niehaus, Architectural Frameworks for MPP System on a Chip, Proceedings of the Third Workshop on Massively Parallel Processing (MPP), April 2003, Nice, France. Image:Mpp.pdf